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【Crack Hack】 register DL : 0: register 和decode 对就的注册机的源码，VC-register and decode to on registration machine source code, VC
Update : 2008-10-13 Size : 15329 Publisher : 张灵飞
【Other resource】 register reallocation DL : 0: 关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
Update : 2008-10-13 Size : 121641 Publisher : 咱航
【ADO-ODBC】 register-login-manager-system-base-on-authority-co DL : 0: 基于权限控制-登陆注册-register-login-manager-system-系统数据库是SQL2000或者ACCESS 还没调试可做参考完整版的到时可以联系transient126@126.com _——————免费学习用的
Update : 2008-10-13 Size : 266777 Publisher : transientlee
【Other】 How to register and download OPNET 9.1 DL : 0: How to register and download OPNET 9.1
Update : 2011-07-27 Size : 91608 Publisher : vampirespit
【ActiveX/DCOM/ATL】 reg DL : 0: Register/Unregister com server
Update : 2024-04-25 Size : 2048 Publisher : 站长
【OS program】 CRegKey DL : 0: 处理Register项的类 -The class for dealing with register item
Update : 2024-04-25 Size : 2048 Publisher : 站长
【SourceCode】 register DL : 0: 一个作业题：链表的建立，查找。-An operating title: the establishment list to find.
Update : 2024-04-25 Size : 2048 Publisher : shijijiang
【Crack Hack】 register DL : 0: register 和decode 对就的注册机的源码，VC-register and decode to on registration machine source code, VC
Update : 2024-04-25 Size : 270336 Publisher : 张灵飞
【Crack Hack】 Register DL : 0: 包括注册号生成软件、LIB、DLL 加密模块各种语言调用加密模块的例子程序等-including registration generation software, LIB, DLL encryption modules in various languages called encryption module examples procedures
Update : 2024-04-25 Size : 184320 Publisher : 张
【VHDL-FPGA-Verilog】 register reallocation DL : 0: 关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
Update : 2024-04-25 Size : 121856 Publisher :
【GIS program】 register DL : 0: 32×32的寄存器堆，它有32个32位的寄存器、两个读端口和一个写端口。该寄存器堆由3个层次共5个模块构成，最低层次的模块是D触发器，中间层次的模块包括32位寄存器、5位地址译码器、32选1多路选通器，顶层模块是寄存器堆模块。设计采用行为建模和结构建模相结合的方法，先用行为建模方法建立低层模块，然后再用结构建模方法搭建高层模块。-32 × 32 of the register file, it has 32 32-bit registers, two read ports and one write port. The register file by the three levels of a total of five modules, the lowest level module is the D flip-flop, middle-level module including 32-bit register, address decoder 5, 32 election more than one way strobe, and top-level module is Register File module. Design using behavioral modeling and structural modeling method of combining the first act of modeling methods used to establish low-level modules, then the structural modeling method to build high-level module.
Update : 2024-04-25 Size : 4096 Publisher : 甜
【Software Engineering】 WM8976Path-and-register-Setting DL : 0: 详述了wm8976的内部结构以及各种外部接口的初始化代码-寄存器配置。附图说明。-Wm8976 detailed internal structure, as well as various external interface initialization code- register configuration. Please refer to Plan Description.
Update : 2024-04-25 Size : 544768 Publisher : yaoqy
【GIS program】 shift-register-sequences DL : 0: 一本介绍产生移位寄存器序列的经典书籍！欢迎下载阅读-Introduce a shift register sequence generated classic books! Welcome to download reading
Update : 2024-04-25 Size : 1974272 Publisher : 李俊
【Other Web Code】 register DL : 0: extjs java oracle register page working
Update : 2024-04-25 Size : 423936 Publisher : vipin
【Other】 register DL : 0: 计算机组成原理实验通用寄存器组。仅供大家参考。-Computer Organization experimental general-purpose register group. Only for your reference.
Update : 2024-04-25 Size : 284672 Publisher : 于洪宇
【Special Effects】 register DL : 0: Image registration used to register images.
Update : 2024-04-25 Size : 1024 Publisher : thrasherx
【Com Port】 Register DL : 0: windows串口控件注册机，及源代码，小程序一个，需要注册控件代码的同学可参考。主要获取注册函数DllRegisterServer 地址-windows serial port control, RI, and source code, a small program, students need to register the control code can refer to. Get registered address of the main function DllRegisterServer
Update : 2024-04-25 Size : 1657856 Publisher : Oscar
【VHDL-FPGA-Verilog】 register-vcode DL : 0: shift register verilog code
Update : 2024-04-25 Size : 6144 Publisher : praveen
【VHDL-FPGA-Verilog】 Shift-register DL : 0: 两种移位寄存器——通用和桶形移位寄存器，用硬件描述语言Verilog编写，适合初学者。-Two kinds of shift register- common and barrel shift register in Verilog hardware description language, suitable for beginners
Update : 2024-04-25 Size : 2048 Publisher : 李菲
【Other】 Register DL : 0: this code is by VHDL language for register ent counter register and
Update : 2024-04-25 Size : 375808 Publisher : nasser

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