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【Other resource】 fifo-ram DL : 0: 采用Verilog语言描述的FIFO和双端口RAM源代码。
Update : 2008-10-13 Size : 762 Publisher : 蒋大为
【VHDL-FPGA-Verilog】同步FIFO设计 DL : 0: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示。
Update : 2010-11-04 Size : 1302250 Publisher : lavien520@163.com
【VHDL-FPGA-Verilog】 fifo的vhdl原代码 DL : 0: 本文为verilog的源代码-In this paper, the source code for Verilog
Update : 2024-04-19 Size : 22528 Publisher : 艾霞
【Other】 verilog_fifo DL : 0: verilog fifo
Update : 2024-04-19 Size : 4096 Publisher : 王新
【VHDL-FPGA-Verilog】一些VHDL源代码 DL : 0: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Update : 2024-04-19 Size : 45056 Publisher : 蔡孟颖
【VHDL-FPGA-Verilog】 my_ramlib_06 DL : 0: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Update : 2024-04-19 Size : 615424 Publisher : ruan
【VHDL-FPGA-Verilog】 ram DL : 0: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Update : 2024-04-19 Size : 2048 Publisher : nick
【Other Embeded program】 fifo-ram DL : 0: 采用Verilog语言描述的FIFO和双端口RAM源代码。-Verilog language used to describe the FIFO and dual-port RAM source code.
Update : 2024-04-19 Size : 1024 Publisher : 蒋大为
【Compress-Decompress algrithms】 fifo DL : 0: FIFO电路(first in，first out)，内部藏有１６ｂｉｔ×１６ｗｏｒｄ的Dual port RAM，依次读出已经写入的数据。因为不存在Address输入，所以请自行设计内藏的读写指针。由FIFO电路输出的EF信号(表示RAM内部的数据为空)和FF信号(表示RAM内部的数据为满)来表示RAM内部的状态，并且控制FIFO的输入信号WEN(写使能)和REN(读使能)。以及为了更好得控制FIFO电路，AEF(表示RAM内部的数据即将空)信号也同时输出。-FIFO circuit (first in, first out), internal possession of 16bit × 16word the Dual port RAM, in order to read out has been written into the data. Address because there is no input, so please read and write their own design containing the pointer. By the FIFO circuit output signal of the EF (express the internal data RAM is empty) and the FF signal (that the internal data RAM or above) to express the state of internal RAM and FIFO control of the input signal WEN (Write Enable) and REN ( Reading-enabled). As well as a control in order to better FIFO circuit, AEF (express the internal data RAM is about to air) signal output at the same time.
Update : 2024-04-19 Size : 1024 Publisher : 史先生
【VHDL-FPGA-Verilog】 ramlib_06 DL : 0: 这是一个有关FIFO的VHDL 程序。。。请大家下载分享。-This is a FIFO of the VHDL program. . . Please download the U.S. share.
Update : 2024-04-19 Size : 577536 Publisher : 张亚伟
【OS Develop】 FIFO DL : 0: fifo.v verilog实现的先进先出存储器-fifo.vverilog realize the FIFO memory
Update : 2024-04-19 Size : 2048 Publisher : patrick
【VHDL-FPGA-Verilog】 fifo DL : 1: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Update : 2024-04-19 Size : 1024 Publisher : shili
【SCM】 FIFO DL : 0: FIFO中文应用笔记，对学习单片机RAM、大量数据处理很有帮助。-FIFO notes
Update : 2024-04-19 Size : 1136640 Publisher : chenlei
【VHDL-FPGA-Verilog】 connect20090223 DL : 0: fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
Update : 2024-04-19 Size : 468992 Publisher : 张菁
【VHDL-FPGA-Verilog】 ram DL : 0: a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
Update : 2024-04-19 Size : 1024 Publisher : sri
【VHDL-FPGA-Verilog】 fpga.fifo DL : 0: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Update : 2024-04-19 Size : 81920 Publisher : 雷志
【Other】 FIFORAM DL : 0: FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
Update : 2024-04-19 Size : 331776 Publisher : SMILE
【VHDL-FPGA-Verilog】 fifo_test DL : 0: FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
Update : 2024-04-19 Size : 2048 Publisher : saul
【Other】 maxii_sch DL : 0: 采用EPM570作为核心，外接FIFO，RAM。可进行数据采集，采用60M时钟的ADC ADS830E。ADC前端电路需要改为差分输入方式以减小电路噪声。该电路经过实际检验可以使用，需要将JTAG电阻改为220以下或者短接。-EPM570 used as a core, external FIFO, RAM. Can be a data collection, using 60M clock ADC ADS830E. ADC front-end circuit differential input methods need to be changed to reduce the circuit noise. The circuit is subject to practical tests can be used needs to be changed to 220 the following JTAG resistance or shorted.
Update : 2024-04-19 Size : 14336 Publisher : zhuyi
【VHDL-FPGA-Verilog】 FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta DL : 0: FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
Update : 2024-04-19 Size : 16619520 Publisher : Aleks

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