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【VHDL-FPGA-Verilog】 DDR（双速率）SDRAM控制器参考设计verilog代码 DL : 0: DDR SDRAM reference design documentation
Update : 2010-09-25 Size : 895281 Publisher : tony_gx@hotmail.com
【Other】 DDR内存布线指导 DL : 0: Freescale 发布的 DDR内存PCB布线指导
Update : 2011-03-01 Size : 756566 Publisher : smartdo
【VHDL-FPGA-Verilog】 Xilinx spartan 6 DDR 测试源代码 DL : 1: Xilinx FPGA Spartan 6 上可运行的软核microblaze以及外设DDR, SPI,UART等测试代码
Update : 2011-09-22 Size : 18476664 Publisher : jameszhou9019
【VHDL-FPGA-Verilog】 ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Update : 2024-04-20 Size : 1031168 Publisher : 包盛花
【Other】 ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2024-04-20 Size : 437248 Publisher : kevin
【VHDL-FPGA-Verilog】 ddr DL : 0: ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
Update : 2024-04-20 Size : 1022976 Publisher : yuling
【VHDL-FPGA-Verilog】 leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Update : 2024-04-20 Size : 114688 Publisher :
【VHDL-FPGA-Verilog】 cpu-leon3-altera-ep2s60-ddr DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Update : 2024-04-20 Size : 752640 Publisher : zhao onely
【DSP program】 ddr DL : 0: davincievm 6446 記憶體DDR撿測-davincievm 6446 seized DDR memory test
Update : 2024-04-20 Size : 48128 Publisher : 謝震威
【Software Engineering】 DDR DL : 1: 关于DDR SDRAM的详细原理和时序分析,对于开发设计有很大使用价值-DDR SDRAM on detailed principles and timing analysis, design for the development of a great value
Update : 2024-04-20 Size : 2201600 Publisher : 王平
【VHDL-FPGA-Verilog】 ref-ddr-sdram-vhdl DL : 0: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Update : 2024-04-20 Size : 1031168 Publisher : wfs
【VHDL-FPGA-Verilog】 ddr DL : 0: 关于ddr sdram的一篇不错的文章，讲得挺详细的。-a good paper about ddr sdram，teaching you how to use ddr sdram.
Update : 2024-04-20 Size : 57344 Publisher : 张涛
【Other】 wb-ddr DL : 0: 基于Wishbone总线的DDR控制器. -A wraper of DDR controller for wishbone bus.
Update : 2024-04-20 Size : 53248 Publisher : bob
【VHDL-FPGA-Verilog】 ddr-sdram--chengxu DL : 0: ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
Update : 2024-04-20 Size : 14336 Publisher : 张杰
【VHDL-FPGA-Verilog】 ddr-sdram DL : 0: DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
Update : 2024-04-20 Size : 923648 Publisher : runxin
【DSP program】 ddr DL : 0: 合众达DM6446试验箱学习实验源代码 ddr内存实验-the experimental source code DM6446 chamber ddr memory test
Update : 2024-04-20 Size : 71680 Publisher : Daniel
【Windows Develop】 DDR DL : 0: DDR内存条的设计资料，PC1600 and PC 21-DDR memory design data, PC1600 and PC 2100
Update : 2024-04-20 Size : 340992 Publisher : minyi
【Windows Develop】 DDR DL : 0: 开发DDR很有价值得开发资料希望对大家有点帮助 -Development of the developers of DDR valuable information we hope a little help
Update : 2024-04-20 Size : 404480 Publisher : 位小记
【DSP program】 ddr DL : 0: 该程序是TI的达芬奇处理器DM6467开发板的DDR测试程序，该程序的开发环境是CCS3.3，使用的编程语言是C-The program is for TI s DaVinci processor DM6467 development board test program of DDR , the program s development environment is CCS3.3, using the programming language is C
Update : 2024-04-20 Size : 58368 Publisher : 何波
【VHDL-FPGA-Verilog】 ddr DL : 0: DDR SDRAM 控制器 VHDL代码，可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus
Update : 2024-04-20 Size : 9216 Publisher : chen

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