This is a design using Verilog language and the digital frequency of the source code, upload click for U.S. research

main
....\cmp_state.ini
....\counter.v
....\data_mux.v
....\db
....\..\main.asm.qmsg
....\..\main.cmp.cdb
....\..\main.cmp.ddb
....\..\main.cmp.hdb
....\..\main.cmp.rdb
....\..\main.cmp.tdb
....\..\main.cmp0.ddb
....\..\main.db_info
....\..\main.eco.cdb
....\..\main.eds_overflow
....\..\main.fit.qmsg
....\..\main.hier_info
....\..\main.hif
....\..\main.map.cdb
....\..\main.map.hdb
....\..\main.map.qmsg
....\..\main.pre_map.cdb
....\..\main.pre_map.hdb
....\..\main.psp
....\..\main.rtlv.hdb
....\..\main.rtlv_sg.cdb
....\..\main.rtlv_sg_swap.cdb
....\..\main.sgdiff.cdb
....\..\main.sgdiff.hdb
....\..\main.sim.hdb
....\..\main.sim.qmsg
....\..\main.sim.rdb
....\..\main.sim.vwf
....\..\main.sld_design_entry.sci
....\..\main.sld_design_entry_dsc.sci
....\..\main.syn_hier_info
....\..\main.tan.qmsg
....\..\main_cmp.qrpt
....\..\main_sim.qrpt
....\dispdecoder.v
....\dispselect.v
....\fdiv.v
....\flip_latch.v
....\gate_control.v
....\main.asm.rpt
....\main.bdf
....\main.done
....\main.fit.eqn
....\main.fit.rpt
....\main.fit.summary
....\main.flow.rpt
....\main.map.eqn
....\main.map.rpt
....\main.map.summary
....\main.pin
....\main.pof
....\main.qpf
....\main.qsf
....\main.qws
....\main.sim.rpt
....\main.tan.rpt
....\main.tan.summary
....\main.v
....\main.vwf

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