VerilogHDL use language to achieve the development of hardware simulation, this procedure is to achieve a static simulation of digital tube display

静态数码显示
............\db
............\..\add_sub_dph.tdf
............\..\add_sub_l0f.tdf
............\..\lpm_constant_mi3.tdf
............\..\sled.asm.qmsg
............\..\sled.cbx.xml
............\..\sled.cmp.cdb
............\..\sled.cmp.hdb
............\..\sled.cmp.rdb
............\..\sled.cmp.tdb
............\..\sled.cmp0.ddb
............\..\sled.db_info
............\..\sled.eco.cdb
............\..\sled.eds_overflow
............\..\sled.fit.qmsg
............\..\sled.fnsim.cdb
............\..\sled.fnsim.hdb
............\..\sled.hier_info
............\..\sled.hif
............\..\sled.map.cdb
............\..\sled.map.hdb
............\..\sled.map.qmsg
............\..\sled.pre_map.cdb
............\..\sled.pre_map.hdb
............\..\sled.psp
............\..\sled.rtlv.hdb
............\..\sled.rtlv_sg.cdb
............\..\sled.rtlv_sg_swap.cdb
............\..\sled.sgdiff.cdb
............\..\sled.sgdiff.hdb
............\..\sled.sim.hdb
............\..\sled.sim.qmsg
............\..\sled.sim.vwf
............\..\sled.sld_design_entry.sci
............\..\sled.sld_design_entry_dsc.sci
............\..\sled.syn_hier_info
............\..\sled.tan.qmsg
............\..\sled_cmp.qrpt
............\..\sled_sim.qrpt
............\sled.asm.rpt
............\sled.done
............\sled.fit.eqn
............\sled.fit.rpt
............\sled.fit.summary
............\sled.flow.rpt
............\sled.map.eqn
............\sled.map.rpt
............\sled.map.summary
............\sled.pin
............\sled.pof
............\sled.qpf
............\sled.qsf
............\sled.sim.rpt
............\sled.tan.rpt
............\sled.tan.summary
............\sled.v
............\sled.vwf

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