Title: adder Download
 Description: verilog adder
 Downloaders recently: [More information of uploader lanshuming]]
 To Search: adder
  • [flowadd] - 32-bit Floating Point Addition Written i
  • [verilog] - Example Collection contains verilog lang
File list (Click to check if it's the file you need, and recomment it at the bottom):
鍔犳硶鍣ㄥ疄楠屼緥绋嬪強鏂囨。
....................\adder
....................\.....\adder.prj
....................\.....\component
....................\.....\constraint
....................\.....\coreconsole
....................\.....\designer
....................\.....\........\impl1
....................\.....\........\.....\adder.adb
....................\.....\........\.....\adder.dtf
....................\.....\........\.....\.........\verify.log
....................\.....\........\.....\adder.ide_des
....................\.....\........\.....\adder.pdb
....................\.....\........\.....\adder.pdb.depends
....................\.....\........\.....\adder.tcl
....................\.....\........\.....\adder_fp
....................\.....\........\.....\........\$$FlashPro_FPBBALTLPT1.L$$
....................\.....\........\.....\........\adder.log
....................\.....\........\.....\........\adder.pro
....................\.....\........\.....\........\projectData
....................\.....\........\.....\........\...........\adder.pdb
....................\.....\........\.....\designer.log
....................\.....\........\.....\full_adder.adb
....................\.....\........\.....\full_adder.ide_des
....................\.....\........\.....\full_adder.tcl
....................\.....\........\.....\half_adder.adb
....................\.....\........\.....\half_adder.ide_des
....................\.....\........\.....\half_adder.tcl
....................\.....\........\.....\simulation
....................\.....\hdl
....................\.....\...\adder.v
....................\.....\...\full_adder.v
....................\.....\...\half_adder.v
....................\.....\phy_synthesis
....................\.....\simulation
....................\.....\..........\modelsim.ini
....................\.....\..........\modelsim.ini.sav
....................\.....\smartgen
....................\.....\........\smartgen.aws
....................\.....\stimulus
....................\.....\synthesis
....................\.....\.........\adder.areasrr
....................\.....\.........\adder.edn
....................\.....\.........\adder.map
....................\.....\.........\adder.pdc
....................\.....\.........\adder.sdf
....................\.....\.........\adder.so
....................\.....\.........\adder.srd
....................\.....\.........\adder.srm
....................\.....\.........\adder.srr
....................\.....\.........\adder.srs
....................\.....\.........\adder.szr
....................\.....\.........\adder.tlg
....................\.....\.........\adder_sdc.sdc
....................\.....\.........\adder_syn.prj
....................\.....\.........\backup
....................\.....\.........\coreip
....................\.....\.........\full_adder.areasrr
....................\.....\.........\full_adder.edn
....................\.....\.........\full_adder.map
....................\.....\.........\full_adder.pdc
....................\.....\.........\full_adder.sdf
....................\.....\.........\full_adder.so
....................\.....\.........\full_adder.srd
....................\.....\.........\full_adder.srm
....................\.....\.........\full_adder.srr
....................\.....\.........\full_adder.srs
....................\.....\.........\full_adder.szr
....................\.....\.........\full_adder.tlg
....................\.....\.........\full_adder_sdc.sdc
....................\.....\.........\full_adder_syn.prj
....................\.....\.........\half_adder.areasrr
....................\.....\.........\half_adder.edn
....................\.....\.........\half_adder.map
....................\.....\.........\half_adder.pdc
....................\.....\.........\half_adder.sdf
....................\.....\.........\half_adder.so
....................\.....\.........\half_adder.srd
....................\.....\.........\half_adder.srm
....................\.....\.........\half_adder.srr
....................\.....\.........\half_adder.srs
....................\.....\.........\half_adder.szr
.....

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