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  • Update : 2008-10-13
  • Size : 18.04kb
  • Downloaded :0次
  • Author :陶玉辉
  • About : 陶玉辉
  • PS : If download it fails, try it again. Download again for free!
Introduction - If you have any usage issues, please Google them yourself
strongly recommend downloading Verilog state machine example. In modelsim running.
Packet file list
(Preview for download)
Packet : 774336408.10.rar filelist
8.10\work\_info
8.10\work\dflop\_primary.vhd
8.10\work\dflop\verilog.asm
8.10\work\dflop\_primary.dat
8.10\work\dflop
8.10\work\shifter\_primary.vhd
8.10\work\shifter\verilog.asm
8.10\work\shifter\_primary.dat
8.10\work\shifter
8.10\work\test\_primary.vhd
8.10\work\test\verilog.asm
8.10\work\test\_primary.dat
8.10\work\test
8.10\work
8.10\vsim.wlf
8.10\dflop.cr.mti
8.10\dflop.mpf
8.10\dflop.v
8.10\dflop.v.bak
8.10\test.v
8.10\test.v.bak
8.10
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