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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 1.47mb
  • Downloaded :0次
  • Author :馬旧
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
ALTERA i2c host/device
Packet file list
(Preview for download)
mi2c
....\docs
....\....\docs.readme
....\....\mi2c_pd.pdf
....\....\mi2c_ps.pdf
....\mi2c.readme
....\verilog
....\.......\gate_sim
....\.......\........\comp_altera_lib.do
....\.......\........\comp_gate.do
....\.......\........\gate_sim.readme
....\.......\........\mi2c_tb.bat
....\.......\........\mi2c_tb.do
....\.......\........\mi2c_tb.ref
....\.......\........\mi2c_tb.scr
....\.......\........\mi2c_tb_diff.bat
....\.......\........\mi2c_tb_diff.scr
....\.......\........\work
....\.......\........\....\mi2c_tb
....\.......\........\....\.......\verilog.asm
....\.......\........\....\.......\_primary.dat
....\.......\........\....\.......\_primary.vhd
....\.......\........\....\_info
....\.......\rtl_encrypted
....\.......\.............\m3s001br.v
....\.......\.............\m3s001br.v.old
....\.......\.............\m3s002br.v
....\.......\.............\m3s002br.v.old
....\.......\.............\m3s003br.v
....\.......\.............\m3s003br.v.old
....\.......\.............\m3s004br.v
....\.......\.............\m3s004br.v.old
....\.......\.............\m3s005br.v
....\.......\.............\m3s005br.v.old
....\.......\.............\m3s006br.v
....\.......\.............\m3s006br.v.old
....\.......\.............\m3s007br.v
....\.......\.............\m3s007br.v.old
....\.......\.............\m3s008br.v
....\.......\.............\m3s008br.v.old
....\.......\.............\m3s009br.v
....\.......\.............\m3s009br.v.old
....\.......\.............\m3s010br.v
....\.......\.............\m3s010br.v.old
....\.......\.............\m3s011br.v
....\.......\.............\m3s011br.v.old
....\.......\.............\mi2c.v
....\.......\.............\mi2c.v.old
....\.......\.............\rtl_encrypted.readme
....\.......\rtl_sim
....\.......\.......\mi2c_tb.bat
....\.......\.......\mi2c_tb.do
....\.......\.......\mi2c_tb.ref
....\.......\.......\mi2c_tb.scr
....\.......\.......\mi2c_tb_diff.bat
....\.......\.......\mi2c_tb_diff.scr
....\.......\.......\rtl_sim.readme
....\.......\.......\work
....\.......\.......\....\m3s001br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s002br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s003br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s004br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s005br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s006br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s007br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s008br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s009br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s010br
....\.......\.......\....\........\verilog.asm
....\.......\.......\....\........\_primary.dat
....\.......\.......\....\........\_primary.vhd
....\.......\.......\....\m3s011br
....\.......\.......\....\........\verilog.asm
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