achieve PCs keyboard (p/s2 Interface) with 8-bit microcontroller connectivity principles : Then in the keyboard clock p3.2 mouth, both of 8051 int0 external interrupts, p1.0 keyboard data received on each button, the keyboard will be made to pulse so SCM SCM external interrupt occurred, data p1.0 I come in a one-to-data formats : a starting place (0), 8 data bits (which keys on the general code, used to identify keys), a parity bit (odd check) at the end of one (1) To achieve : keyboard will be sent back data in a buffer (the array) When the button after internal disruption to address shortcomings on the button : As the 51 SCM buffer capacity is limited not so much open, This has led to record the number of keys of the keyboard is too small, that is fault-tolerant general. However, if the

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c51jing.doc

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