Using VHDL language, on Altera s DE2 development board for development, which in this case the realization of paragraph 7 of the on-board digital tube display, in niosiiIDE hardware implementation based on a small circle of bright lights out

Packet : 99273868test.rar filelist
test\bin27seg.bsf
test\bin27seg.vhd
test\db\prev_cmp_seg7test.map.qmsg
test\db\seg7test.(0).cnf.cdb
test\db\seg7test.(0).cnf.hdb
test\db\seg7test.cbx.xml
test\db\seg7test.cmp.rdb
test\db\seg7test.dbp
test\db\seg7test.db_info
test\db\seg7test.eco.cdb
test\db\seg7test.hier_info
test\db\seg7test.hif
test\db\seg7test.map.bpm
test\db\seg7test.map.cdb
test\db\seg7test.map.ecobp
test\db\seg7test.map.hdb
test\db\seg7test.map.logdb
test\db\seg7test.map.qmsg
test\db\seg7test.map_bb.cdb
test\db\seg7test.map_bb.hdb
test\db\seg7test.map_bb.logdb
test\db\seg7test.pre_map.cdb
test\db\seg7test.pre_map.hdb
test\db\seg7test.psp
test\db\seg7test.pss
test\db\seg7test.rtlv.hdb
test\db\seg7test.rtlv_sg.cdb
test\db\seg7test.rtlv_sg_swap.cdb
test\db\seg7test.sgdiff.cdb
test\db\seg7test.sgdiff.hdb
test\db\seg7test.sld_design_entry.sci
test\db\seg7test.sld_design_entry_dsc.sci
test\db\seg7test.syn_hier_info
test\prev_cmp_seg7test.qmsg
test\seg7test.done
test\seg7test.flow.rpt
test\seg7test.map.rpt
test\seg7test.map.summary
test\seg7test.qpf
test\seg7test.qsf
test\seg7test.qws
test\db
test

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