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  • Update : 2008-10-13
  • Size : 62.22kb
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  • Author :zys
  • About : zys
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Introduction - If you have any usage issues, please Google them yourself
USB 1.1 in Verilog code, has passed through FPGA verification
Packet file list
(Preview for download)
Packet : 79419091usb1.1.rar filelist
usb1.1\usb1_1_deviceip\testbench\tests.v
usb1.1\usb1_1_deviceip\testbench\tests_lib.v
usb1.1\usb1_1_deviceip\testbench\test_bench_top.v
usb1.1\usb1_1_deviceip\testbench\timescale.v
usb1.1\usb1_1_deviceip\sim\sim1.txt
usb1.1\usb1_1_deviceip\sim\sim2.txt
usb1.1\usb1_1_deviceip\sim\sim3.txt
usb1.1\usb1_1_deviceip\RTL_code\timescale.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_core.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_crc16.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_crc5.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_ctrl.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_defines.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_fifo2.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_idma.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_pa.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_pd.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_pe.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_pl.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_rom1.v
usb1.1\usb1_1_deviceip\RTL_code\usb1_utmi_if.v
usb1.1\usb1_1_deviceip\doc\read_me_1.1.txt
usb1.1\usb1_1_deviceip\doc\read_me_1.2.txt
usb1.1\usb1_1_deviceip\doc\sucess_story.txt
usb1.1\USB1_1 PHY\timescale.v
usb1.1\USB1_1 PHY\USB 1.1 PHY.txt
usb1.1\USB1_1 PHY\usb_phy.v
usb1.1\USB1_1 PHY\usb_rx_phy.v
usb1.1\USB1_1 PHY\usb_tx_phy.v
usb1.1\usb1_1_deviceip\testbench
usb1.1\usb1_1_deviceip\sim
usb1.1\usb1_1_deviceip\RTL_code
usb1.1\usb1_1_deviceip\doc
usb1.1\usb1_1_deviceip
usb1.1\USB1_1 PHY
usb1.1
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