This procedure for the Verilog control ADC all procedures can be applied to test

Packet : 5956485adcontrol.rar filelist
ADControl\block1.qpf
ADControl\block1.qsf
ADControl\ad_control.v
ADControl\block1.done
ADControl\ad_control.bsf
ADControl\block1.bdf
ADControl\block1.map.rpt
ADControl\block1.flow.rpt
ADControl\block1.map.summary
ADControl\block1.pin
ADControl\block1.fit.rpt
ADControl\block1.fit.smsg
ADControl\block1.fit.summary
ADControl\block1.asm.rpt
ADControl\block1.tan.summary
ADControl\block1.tan.rpt
ADControl\block1.vwf
ADControl\block1.sim.rpt
ADControl\block1.bsf
ADControl\db\wed.zsf
ADControl\db\block1.sim.vwf
ADControl\db\lpm_divide_g8m.tdf
ADControl\db\sign_div_unsign_9nh.tdf
ADControl\db\alt_u_div_2ue.tdf
ADControl\db\add_sub_3dc.tdf
ADControl\db\add_sub_4dc.tdf
ADControl\db\add_sub_kec.tdf
ADControl\db\add_sub_lec.tdf
ADControl\db\add_sub_mec.tdf
ADControl\db\add_sub_nec.tdf
ADControl\db\add_sub_oec.tdf
ADControl\db\add_sub_pec.tdf
ADControl\db\add_sub_qec.tdf
ADControl\db\add_sub_rec.tdf
ADControl\db\add_sub_sec.tdf
ADControl\db\add_sub_tec.tdf
ADControl\db\add_sub_5dc.tdf
ADControl\db\add_sub_uec.tdf
ADControl\db\add_sub_vec.tdf
ADControl\db\add_sub_0fc.tdf
ADControl\db\add_sub_1fc.tdf
ADControl\db\add_sub_2fc.tdf
ADControl\db\add_sub_3fc.tdf
ADControl\db\add_sub_4fc.tdf
ADControl\db\add_sub_5fc.tdf
ADControl\db\add_sub_6fc.tdf
ADControl\db\add_sub_7fc.tdf
ADControl\db\add_sub_6dc.tdf
ADControl\db\add_sub_8fc.tdf
ADControl\db\add_sub_9fc.tdf
ADControl\db\add_sub_7dc.tdf
ADControl\db\add_sub_8dc.tdf
ADControl\db\add_sub_9dc.tdf
ADControl\db\add_sub_adc.tdf
ADControl\db\add_sub_bdc.tdf
ADControl\db\add_sub_jec.tdf
ADControl\db\add_sub_mac.tdf
ADControl\db\block1.db_info
ADControl\db\wed.wsf
ADControl\db\block1.sld_design_entry.sci
ADControl\db\block1.eco.cdb
ADControl\block1_assignment_defaults.qdf
ADControl\block1.qws
ADControl\db
ADControl

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