Title: uvm_ref Download
  • Category:
  • Other systems
  • Platform:
  • C/C++
  • File Size:
  • 5106688
  • Update:
  • 2021-02-13
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  • Uploaded by:
  • peaceyang
 Description: Implementation of UVM verification platform, simple Verilog verification platform, including reference platform, UART interface implementation
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文件名大小更新时间
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\ahb2apb\rtl\ahb2apb.f 852 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\ahb2apb\rtl\ahb2apb.irunargs 74 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\ahb2apb\rtl\ahb2apb.v 16935 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\ahb2apb\rtl\ahb2apb_bug.irunargs 919 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\ahb2apb\rtl\ahb2apb_defines.v 1138 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\ahb2apb\rtl\ahb2apb_lab1.v 17809 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\alut\rtl\alut.irunargs 389 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\alut\rtl\alut.v 7719 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\alut\rtl\alut_addr_checker.v 12790 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\alut\rtl\alut_age_checker.v 11544 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\alut\rtl\alut_defines.v 1717 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\alut\rtl\alut_mem.v 3028 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\alut\rtl\alut_reg_bank.v 12634 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\alut_veneer.v 3229 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\apb_subs.filelist 1297 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\apb_subsystem.f 1850 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\apb_subsystem.irunargs 837 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\apb_subsystem_0.v 35916 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\apb_subsystem_1.v 6735 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\apb_subsystem_bug.irunargs 840 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\gpio_veneer.v 5350 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\power_ctrl_veneer.v 16210 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\smc_veneer.v 7276 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\spi_veneer.v 7716 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\ttc_veneer.v 3817 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\uart0_veneer.v 6357 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\rtl\uart1_veneer.v 6337 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\topologies\all_apb_black_boxed.topology 274 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\topologies\uart0_not_black_boxed.topology 299 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\topologies\uart0_uart1_not_black_boxed.topology 355 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\topologies\uart1_not_black_boxed.topology 299 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\apb_subsystem\topologies\uart_not_black_boxed.topology 299 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_busmatrix\arbiter.v 2954 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_busmatrix\bm_defs.v 2590 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_busmatrix\bm_params.v 2660 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_busmatrix\busmatrix.irunargs 140 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_busmatrix\busmatrix.v 88479 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_busmatrix\master_if.v 14920 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_busmatrix\multiplexer.v 3735 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_busmatrix\req_register.v 10662 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_busmatrix\slave_if.v 11440 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\cpf\cdn_chip.cpf 35530 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\rtl\ahb2ocp.v 16614 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\rtl\ahb2ocp_defs.v 1179 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\rtl\ahb2ocp_ram.v 2523 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\rtl\cdn_chip_top.irunargs 1359 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\rtl\cdn_chip_top.v 66850 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\rtl\ocp_rtl.conf 3790 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\topologies\ahb_bus_only.topology 143 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\topologies\apb_and_mipi_black_boxed.topology 69 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\topologies\mipi_only.topology 143 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\cdn_chip\topologies\ocp_and_mipi_black_boxed.topology 60 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma.f 164 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma.irunargs 212 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma.v 41889 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_ahb_config.v 24154 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_ahb_master.v 4826 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_ahb_mux.v 10847 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_apb_mux.v 10119 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_arbiter.v 17007 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_channel.v 49570 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_defs.v 5502 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_flow_mux.v 11260 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_int_control.v 10448 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_rx_sm.v 10559 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\dma\rtl\dma_tx_sm.v 10597 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\gpio\doc\GPIO_UserGuide.pdf 181512 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\gpio\rtl\gpio_lite.f 965 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\gpio\rtl\gpio_lite.irunargs 1032 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\gpio\rtl\gpio_lite.v 5858 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\gpio\rtl\gpio_lite_subunit.v 9080 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\mem_wrap\rtl\ROM_SP_512x32_wrap.v 1413 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\mem_wrap\rtl\SRAM_DP_512x36_wrap.v 4781 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\mem_wrap\rtl\SRAM_DP_64x36_wrap.v 4718 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\mem_wrap\rtl\SRAM_SP_16x128_wrap.v 3395 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\mem_wrap\rtl\SRAM_SP_2kx32_wrap.v 2902 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\mem_wrap\rtl\SRAM_SP_4kx32_wrap.v 1780 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\mem_wrap\rtl\SRAM_SP_512x8_wrap.v 2327 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\mem_wrap\rtl\SRAM_SP_8kx32_wrap.v 2850 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\mem_wrap\rtl\SRAM_SP_ADV_synth.v 1592 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\misc\rtl\generic_dpsram.v 3484 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\misc\rtl\generic_sram.v 2541 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\misc\rtl\generic_sram_bit.v 2691 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\misc\rtl\ldo.vams 10493 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\misc\rtl\vco.vams 1372 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\eth_host.v 4621 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\eth_memory.v 5836 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\eth_phy.v 41421 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\eth_phy_defines.v 4393 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\tb_cop.v 13483 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\tb_ethernet.v 975590 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\tb_ethernet_with_cop.v 19643 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\tb_eth_defines.v 10574 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\tb_eth_top.v 51437 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\wb_bus_mon.v 18743 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\wb_master32.v 13486 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\wb_master_behavioral.v 23268 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\wb_model_defines.v 7223 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\bench\verilog\wb_slave_behavioral.v 12219 2014-04-24
uvm_ref\1.2\uvm_ref_flow_1.2\designs\socv\rtl\rtl_lpw\opencores\ethmac\README.txt 4450 2014-04-24

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