Title: Vivado逻辑门电路 Download
 Description: logic gate circuit files(nand gate, nor gate, xor gate, etc)
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File list (Click to check if it's the file you need, and recomment it at the bottom):
文件名大小更新时间
AND_gate\AND_gate.cache 0 2020-10-13
AND_gate\AND_gate.cache\wt 0 2020-10-13
AND_gate\AND_gate.cache\wt\gui_handlers.wdf 2268 2020-10-13
AND_gate\AND_gate.cache\wt\java_command_handlers.wdf 491 2020-10-13
AND_gate\AND_gate.cache\wt\project.wpc 61 2020-10-13
AND_gate\AND_gate.cache\wt\synthesis.wdf 5390 2020-10-13
AND_gate\AND_gate.cache\wt\synthesis_details.wdf 100 2020-10-13
AND_gate\AND_gate.cache\wt\webtalk_pa.xml 2999 2020-10-13
AND_gate\AND_gate.hw 0 2020-10-13
AND_gate\AND_gate.hw\AND_gate.lpr 290 2020-10-13
AND_gate\AND_gate.ip_user_files 0 2020-10-13
AND_gate\AND_gate.ip_user_files\README.txt 130 2020-10-13
AND_gate\AND_gate.runs 0 2020-10-13
AND_gate\AND_gate.runs\.jobs 0 2020-10-13
AND_gate\AND_gate.runs\.jobs\vrs_config_1.xml 305 2020-10-13
AND_gate\AND_gate.runs\synth_1 0 2020-10-13
AND_gate\AND_gate.runs\synth_1\.vivado.begin.rst 219 2020-10-13
AND_gate\AND_gate.runs\synth_1\.vivado.end.rst 0 2020-10-13
AND_gate\AND_gate.runs\synth_1\.Vivado_Synthesis.queue.rst 0 2020-10-13
AND_gate\AND_gate.runs\synth_1\.Xil 0 2020-10-13
AND_gate\AND_gate.runs\synth_1\__synthesis_is_complete__ 0 2020-10-13
AND_gate\AND_gate.runs\synth_1\AND_gate.dcp 5933 2020-10-13
AND_gate\AND_gate.runs\synth_1\AND_gate.tcl 2261 2020-10-13
AND_gate\AND_gate.runs\synth_1\AND_gate.vds 13873 2020-10-13
AND_gate\AND_gate.runs\synth_1\AND_gate_utilization_synth.pb 242 2020-10-13
AND_gate\AND_gate.runs\synth_1\AND_gate_utilization_synth.rpt 6597 2020-10-13
AND_gate\AND_gate.runs\synth_1\gen_run.xml 1814 2020-10-13
AND_gate\AND_gate.runs\synth_1\htr.txt 393 2020-10-13
AND_gate\AND_gate.runs\synth_1\ISEWrap.js 8379 2020-10-13
AND_gate\AND_gate.runs\synth_1\ISEWrap.sh 1806 2020-10-13
AND_gate\AND_gate.runs\synth_1\project.wdf 3634 2020-10-13
AND_gate\AND_gate.runs\synth_1\rundef.js 1323 2020-10-13
AND_gate\AND_gate.runs\synth_1\runme.bat 229 2020-10-13
AND_gate\AND_gate.runs\synth_1\runme.log 13780 2020-10-13
AND_gate\AND_gate.runs\synth_1\runme.sh 1185 2020-10-13
AND_gate\AND_gate.runs\synth_1\vivado.jou 682 2020-10-13
AND_gate\AND_gate.runs\synth_1\vivado.pb 21732 2020-10-13
AND_gate\AND_gate.sim 0 2020-10-13
AND_gate\AND_gate.srcs 0 2020-10-13
AND_gate\AND_gate.srcs\sources_1 0 2020-10-13
AND_gate\AND_gate.srcs\sources_1\new 0 2020-10-13
AND_gate\AND_gate.srcs\sources_1\new\AND_gate.v 591 2020-10-13
AND_gate\AND_gate.srcs\sources_1\new\component.xml 8101 2020-10-13
AND_gate\AND_gate.srcs\sources_1\new\xgui 0 2020-10-13
AND_gate\AND_gate.srcs\sources_1\new\xgui\AND_gate_v1_0.tcl 205 2020-10-13
AND_gate\AND_gate.xpr 10673 2020-10-13
gates2\gates2.cache 0 2020-10-13
gates2\gates2.cache\compile_simlib 0 2020-10-07
gates2\gates2.cache\compile_simlib\activehdl 0 2020-10-07
gates2\gates2.cache\compile_simlib\ies 0 2020-10-07
gates2\gates2.cache\compile_simlib\modelsim 0 2020-10-07
gates2\gates2.cache\compile_simlib\questa 0 2020-10-07
gates2\gates2.cache\compile_simlib\riviera 0 2020-10-07
gates2\gates2.cache\compile_simlib\vcs 0 2020-10-07
gates2\gates2.cache\compile_simlib\xcelium 0 2020-10-07
gates2\gates2.cache\ip 0 2020-10-07
gates2\gates2.cache\ip\2019.1 0 2020-10-07
gates2\gates2.cache\wt 0 2020-10-07
gates2\gates2.cache\wt\gui_handlers.wdf 6105 2020-10-13
gates2\gates2.cache\wt\java_command_handlers.wdf 1598 2020-10-13
gates2\gates2.cache\wt\project.wpc 61 2020-10-13
gates2\gates2.cache\wt\synthesis.wdf 5385 2020-10-07
gates2\gates2.cache\wt\synthesis_details.wdf 100 2020-10-07
gates2\gates2.cache\wt\webtalk_pa.xml 5885 2020-10-13
gates2\gates2.cache\wt\xsim.wdf 256 2020-10-07
gates2\gates2.hw 0 2020-10-13
gates2\gates2.hw\gates2.lpr 290 2020-10-07
gates2\gates2.ip_user_files 0 2020-10-13
gates2\gates2.ip_user_files\README.txt 130 2020-10-07
gates2\gates2.runs 0 2020-10-13
gates2\gates2.runs\.jobs 0 2020-10-07
gates2\gates2.runs\.jobs\vrs_config_1.xml 301 2020-10-07
gates2\gates2.runs\.jobs\vrs_config_2.xml 301 2020-10-07
gates2\gates2.runs\.jobs\vrs_config_3.xml 315 2020-10-07
gates2\gates2.runs\impl_1 0 2020-10-07
gates2\gates2.runs\impl_1\.init_design.begin.rst 182 2020-10-07
gates2\gates2.runs\impl_1\.init_design.end.rst 0 2020-10-07
gates2\gates2.runs\impl_1\.opt_design.begin.rst 182 2020-10-07
gates2\gates2.runs\impl_1\.opt_design.end.rst 0 2020-10-07
gates2\gates2.runs\impl_1\.place_design.begin.rst 182 2020-10-07
gates2\gates2.runs\impl_1\.place_design.end.rst 0 2020-10-07
gates2\gates2.runs\impl_1\.route_design.begin.rst 182 2020-10-07
gates2\gates2.runs\impl_1\.route_design.end.rst 0 2020-10-07
gates2\gates2.runs\impl_1\.vivado.begin.rst 218 2020-10-07
gates2\gates2.runs\impl_1\.vivado.end.rst 0 2020-10-07
gates2\gates2.runs\impl_1\.Vivado_Implementation.queue.rst 0 2020-10-07
gates2\gates2.runs\impl_1\.Xil 0 2020-10-07
gates2\gates2.runs\impl_1\gates2.dcp 118852 2020-10-07
gates2\gates2.runs\impl_1\gates2.tcl 5241 2020-10-07
gates2\gates2.runs\impl_1\gates2.vdi 24033 2020-10-07
gates2\gates2.runs\impl_1\gates2_bus_skew_routed.pb 30 2020-10-07
gates2\gates2.runs\impl_1\gates2_bus_skew_routed.rpt 859 2020-10-07
gates2\gates2.runs\impl_1\gates2_bus_skew_routed.rpx 1024 2020-10-07
gates2\gates2.runs\impl_1\gates2_clock_utilization_routed.rpt 6473 2020-10-07
gates2\gates2.runs\impl_1\gates2_control_sets_placed.rpt 3410 2020-10-07
gates2\gates2.runs\impl_1\gates2_drc_opted.pb 37 2020-10-07
gates2\gates2.runs\impl_1\gates2_drc_opted.rpt 2330 2020-10-07
gates2\gates2.runs\impl_1\gates2_drc_opted.rpx 1627 2020-10-07
gates2\gates2.runs\impl_1\gates2_drc_routed.pb 37 2020-10-07
gates2\gates2.runs\impl_1\gates2_drc_routed.rpt 2340 2020-10-07

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