Title: 8位verilog加法器 Download
 Description: The detailed scheme design of electronic hardware is worth learning
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文件名大小更新时间
e52_add_4\e52_add_4\add_4.v 796 2017-03-07
e52_add_4\e52_add_4\sim\add_4.cr.mti 554 2017-03-04
e52_add_4\e52_add_4\sim\add_4.mpf 20127 2017-03-04
e52_add_4\e52_add_4\sim\tb_add_4.v 1014 2017-03-07
e52_add_4\e52_add_4\sim\vsim.wlf 73728 2017-03-04
e52_add_4\e52_add_4\sim\work\add_4\verilog.prw 304 2017-03-04
e52_add_4\e52_add_4\sim\work\add_4\verilog.psm 7104 2017-03-04
e52_add_4\e52_add_4\sim\work\add_4\_primary.dat 607 2017-03-04
e52_add_4\e52_add_4\sim\work\add_4\_primary.dbs 672 2017-03-04
e52_add_4\e52_add_4\sim\work\add_4\_primary.vhd 487 2017-03-04
e52_add_4\e52_add_4\sim\work\tb_add_4\verilog.prw 890 2017-03-04
e52_add_4\e52_add_4\sim\work\tb_add_4\verilog.psm 11808 2017-03-04
e52_add_4\e52_add_4\sim\work\tb_add_4\_primary.dat 947 2017-03-04
e52_add_4\e52_add_4\sim\work\tb_add_4\_primary.dbs 1260 2017-03-04
e52_add_4\e52_add_4\sim\work\tb_add_4\_primary.vhd 350 2017-03-04
e52_add_4\e52_add_4\sim\work\_info 835 2017-03-04
e52_add_4\e52_add_4\sim\work\_temp\vlogdnxrre 486 2017-03-04
e52_add_4\e52_add_4\sim\work\_vmake 26 2017-03-04
e52_add_4\e52_add_4\仿真结果.png 19104 2017-03-04
e52_add_4\e52_add_4\sim\work\add_4 0 2017-03-04
e52_add_4\e52_add_4\sim\work\tb_add_4 0 2017-03-04
e52_add_4\e52_add_4\sim\work\_temp 0 2017-03-04
e52_add_4\e52_add_4\sim\work 0 2017-03-04
e52_add_4\e52_add_4\sim 0 2017-03-14
e52_add_4\e52_add_4 0 2017-03-15
e52_add_4 0 2017-03-15

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