Title: _LDPC编译码技术的研究与实现 Download
Description: LDPC decoding algorithm mainly studies BP decoding algorithm based on probability measure, BP decoding algorithm based on LLR, normalized minimum sum decoding algorithm and so on. Finally, the normalized minimum sum decoding algorithm suitable for FPGA hardware implementation is selected. In the aspect of implementation structure, tpmp and tdmp are simulated and compared. Finally, tdmp implementation structure with fast convergence speed and less iteration times is selected, that is horizontal layered iterative structure. The final decoder can achieve BER of 10-6 when SNR is 2.5dB. In addition, in order to achieve the goal of high-speed decoder, ping-pong operation, pipeline structure and simultaneous decoding of four codewords are used to improve the throughput of the decoder.
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