In ccs debug DSP external memory sdram of the anti-color code, mainly through the dsp / bios in the HST pipeline implementation. One choice is the DM642 chip and MT48LC16M16A2 the sdram, sdram and the related timing parameters have been configured.

Packet : 99273909reversalbw64_7.10.rar filelist
reversalBW64_7.10\cc_build_Debug.log
reversalBW64_7.10\Debug.lkf
reversalBW64_7.10\Debug.lkv
reversalBW64_7.10\rBW.cdb
reversalBW64_7.10\rBWcfg.cmd
reversalBW64_7.10\rBWcfg.h
reversalBW64_7.10\rBWcfg.h62
reversalBW64_7.10\rBWcfg.s62
reversalBW64_7.10\rBWcfg_c.c
reversalBW64_7.10\rBWmain.c
reversalBW64_7.10\rBWmain.c.bak
reversalBW64_7.10\reversalBW.paf
reversalBW64_7.10\reversalBW.paf2
reversalBW64_7.10\reversalBW.pjt
reversalBW64_7.10\reversalBW.sbl
reversalBW64_7.10\reversalBW.CS_\FILE.CDX
reversalBW64_7.10\reversalBW.CS_\FILE.DBF
reversalBW64_7.10\reversalBW.CS_\FILE.FPT
reversalBW64_7.10\reversalBW.CS_\SYMBOL.CDX
reversalBW64_7.10\reversalBW.CS_\SYMBOL.DBF
reversalBW64_7.10\reversalBW.CS_\SYMBOL.FPT
reversalBW64_7.10\Debug
reversalBW64_7.10\reversalBW.CS_
reversalBW64_7.10

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