Title: 0_09_uart_tx Download
  • Category:
  • VHDL-FPGA-Verilog
  • Platform:
  • Verilog
  • File Size:
  • 13871104
  • Update:
  • 2020-03-26
  • Downloads:
  • 0
  • Uploaded by:
  • ZDCHXGG
 Description: On the FPGA board, the sending function of the serial port is realized by a single key, and the engineering configuration needs to be modified by the simulation
 Downloaders recently: [More information of uploader ZDCHXGG]]
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File list (Click to check if it's the file you need, and recomment it at the bottom):
文件名大小更新时间
doc 0 2020-03-20
doc\UART串口发送模块设计.docx 757350 2015-09-20
doc\uart发送模块设计.vsdx 40705 2015-09-20
doc\~$RT串口发送模块设计.docx 162 2019-12-29
doc\新建文本文档.txt 26 2020-01-14
img 0 2015-06-29
prj 0 2020-03-26
prj\db 0 2020-03-26
prj\db\altsyncram_4u14.tdf 10720 2019-12-30
prj\db\altsyncram_u024.tdf 19353 2019-12-30
prj\db\altsyncram_ut14.tdf 10714 2019-12-30
prj\db\cmpr_ngc.tdf 1684 2019-12-30
prj\db\cmpr_pgc.tdf 1850 2019-12-30
prj\db\cmpr_qgc.tdf 1916 2019-12-30
prj\db\cmpr_rgc.tdf 2006 2019-12-30
prj\db\cntr_23j.tdf 3298 2019-12-30
prj\db\cntr_89j.tdf 3960 2019-12-30
prj\db\cntr_cgi.tdf 3864 2019-12-30
prj\db\cntr_dgi.tdf 3733 2019-12-30
prj\db\cntr_egi.tdf 3864 2019-12-30
prj\db\cntr_g9j.tdf 4102 2019-12-30
prj\db\cntr_igi.tdf 3864 2019-12-30
prj\db\cntr_o9j.tdf 4365 2019-12-30
prj\db\cntr_sei.tdf 3601 2019-12-30
prj\db\decode_dvf.tdf 1565 2019-12-30
prj\db\logic_util_heursitic.dat 19228 2020-01-14
prj\db\mux_psc.tdf 4429 2019-12-30
prj\db\mux_rsc.tdf 4725 2019-12-30
prj\db\mux_vsc.tdf 5317 2019-12-30
prj\db\prev_cmp_uart_byte_tx.qmsg 75899 2020-01-14
prj\db\uart_byte_tx.db_info 140 2020-03-26
prj\db\uart_byte_tx.ipinfo 265 2020-03-26
prj\db\uart_byte_tx.sld_design_entry.sci 202 2020-03-26
prj\greybox_tmp 0 2020-03-20
prj\greybox_tmp\cbx_args.txt 220 2015-09-20
prj\incremental_db 0 2020-03-20
prj\incremental_db\compiled_partitions 0 2020-03-26
prj\incremental_db\compiled_partitions\uart_byte_tx.db_info 140 2020-03-26
prj\incremental_db\README 653 2015-12-22
prj\issp.qip 293 2015-09-20
prj\issp.v 3931 2015-09-20
prj\issp_bb.v 2892 2015-09-20
prj\simulation 0 2020-03-20
prj\simulation\modelsim 0 2020-03-20
prj\simulation\modelsim\modelsim.ini 90487 2019-12-30
prj\simulation\modelsim\msim_transcript 35419 2019-12-30
prj\simulation\modelsim\rtl_work 0 2020-03-20
prj\simulation\modelsim\rtl_work\@_opt 0 2020-03-20
prj\simulation\modelsim\rtl_work\@_opt\_lib.qdb 49152 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib1_0.qdb 32768 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib1_0.qpg 8192 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib1_0.qtl 89497 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib2_0.qdb 32768 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib2_0.qpg 0 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib2_0.qtl 31668 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib3_0.qdb 32768 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib3_0.qpg 0 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib3_0.qtl 28066 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib4_0.qdb 32768 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib4_0.qpg 32768 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib4_0.qtl 37580 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib5_0.qdb 32768 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib5_0.qpg 40960 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib5_0.qtl 38216 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib6_0.qdb 32768 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib6_0.qpg 24576 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib6_0.qtl 34044 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib7_0.qdb 32768 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib7_0.qpg 24576 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib7_0.qtl 34044 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib8_0.qdb 32768 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib8_0.qpg 40960 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt\_lib8_0.qtl 12245 2019-12-29
prj\simulation\modelsim\rtl_work\@_opt1 0 2020-03-20
prj\simulation\modelsim\rtl_work\@_opt1\_lib.qdb 49152 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib1_0.qdb 32768 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib1_0.qpg 16384 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib1_0.qtl 58110 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib2_0.qdb 32768 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib2_0.qpg 0 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib2_0.qtl 8850 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib3_0.qdb 32768 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib3_0.qpg 0 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib3_0.qtl 8350 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib4_0.qdb 32768 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib4_0.qpg 40960 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib4_0.qtl 49185 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib5_0.qdb 32768 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib5_0.qpg 40960 2019-12-30
prj\simulation\modelsim\rtl_work\@_opt1\_lib5_0.qtl 13403 2019-12-30
prj\simulation\modelsim\rtl_work\_info 3830 2019-12-30
prj\simulation\modelsim\rtl_work\_lib.qdb 49152 2019-12-30
prj\simulation\modelsim\rtl_work\_lib1_0.qdb 32768 2019-12-30
prj\simulation\modelsim\rtl_work\_lib1_0.qpg 0 2019-12-30
prj\simulation\modelsim\rtl_work\_lib1_0.qtl 37772 2019-12-30
prj\simulation\modelsim\rtl_work\_opt__lock 44 2019-12-29
prj\simulation\modelsim\rtl_work\_temp 0 2019-12-30
prj\simulation\modelsim\rtl_work\_tempmsg 0 2019-12-30
prj\simulation\modelsim\rtl_work\_vmake 29 2019-12-30
prj\simulation\modelsim\uart_byte_tx.sft 370 2020-01-14

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