Altera FPGA DDR3 controller test module

02_ddr3_test\coregen.cgc
02_ddr3_test\coregen.cgp
02_ddr3_test\mig_39_2\docs\ug388.pdf
02_ddr3_test\mig_39_2\docs\ug416.pdf
02_ddr3_test\mig_39_2\example_design\chipscope\ax845.cpj
02_ddr3_test\mig_39_2\example_design\datasheet.txt
02_ddr3_test\mig_39_2\example_design\log.txt
02_ddr3_test\mig_39_2\example_design\mig.prj
02_ddr3_test\mig_39_2\example_design\par\coregen.cgc
02_ddr3_test\mig_39_2\example_design\par\coregen.cgp
02_ddr3_test\mig_39_2\example_design\par\coregen.log
02_ddr3_test\mig_39_2\example_design\par\create_ise.bat
02_ddr3_test\mig_39_2\example_design\par\example_top.bgn
02_ddr3_test\mig_39_2\example_design\par\example_top.bit
02_ddr3_test\mig_39_2\example_design\par\example_top.bld
02_ddr3_test\mig_39_2\example_design\par\example_top.cdc
02_ddr3_test\mig_39_2\example_design\par\example_top.cmd_log
02_ddr3_test\mig_39_2\example_design\par\example_top.drc
02_ddr3_test\mig_39_2\example_design\par\example_top.ncd
02_ddr3_test\mig_39_2\example_design\par\example_top.ngc
02_ddr3_test\mig_39_2\example_design\par\example_top.ngd
02_ddr3_test\mig_39_2\example_design\par\example_top.ngr
02_ddr3_test\mig_39_2\example_design\par\example_top.pad
02_ddr3_test\mig_39_2\example_design\par\example_top.par
02_ddr3_test\mig_39_2\example_design\par\example_top.pcf
02_ddr3_test\mig_39_2\example_design\par\example_top.prj
02_ddr3_test\mig_39_2\example_design\par\example_top.ptwx
02_ddr3_test\mig_39_2\example_design\par\example_top.stx
02_ddr3_test\mig_39_2\example_design\par\example_top.syr
02_ddr3_test\mig_39_2\example_design\par\example_top.twr
02_ddr3_test\mig_39_2\example_design\par\example_top.twx
02_ddr3_test\mig_39_2\example_design\par\example_top.ucf
02_ddr3_test\mig_39_2\example_design\par\example_top.unroutes
02_ddr3_test\mig_39_2\example_design\par\example_top.ut
02_ddr3_test\mig_39_2\example_design\par\example_top.xpi
02_ddr3_test\mig_39_2\example_design\par\example_top.xst
02_ddr3_test\mig_39_2\example_design\par\example_top_bitgen.xwbt
02_ddr3_test\mig_39_2\example_design\par\example_top_envsettings.html
02_ddr3_test\mig_39_2\example_design\par\example_top_guide.ncd
02_ddr3_test\mig_39_2\example_design\par\example_top_map.map
02_ddr3_test\mig_39_2\example_design\par\example_top_map.mrp
02_ddr3_test\mig_39_2\example_design\par\example_top_map.ncd
02_ddr3_test\mig_39_2\example_design\par\example_top_map.ngm
02_ddr3_test\mig_39_2\example_design\par\example_top_map.xrpt
02_ddr3_test\mig_39_2\example_design\par\example_top_ngdbuild.xrpt
02_ddr3_test\mig_39_2\example_design\par\example_top_pad.csv
02_ddr3_test\mig_39_2\example_design\par\example_top_pad.txt
02_ddr3_test\mig_39_2\example_design\par\example_top_par.xrpt
02_ddr3_test\mig_39_2\example_design\par\example_top_summary.html
02_ddr3_test\mig_39_2\example_design\par\example_top_summary.xml
02_ddr3_test\mig_39_2\example_design\par\example_top_usage.xml
02_ddr3_test\mig_39_2\example_design\par\example_top_xst.xrpt
02_ddr3_test\mig_39_2\example_design\par\icon.asy
02_ddr3_test\mig_39_2\example_design\par\icon.gise
02_ddr3_test\mig_39_2\example_design\par\icon.ngc
02_ddr3_test\mig_39_2\example_design\par\icon.xco
02_ddr3_test\mig_39_2\example_design\par\icon_coregen.xco
02_ddr3_test\mig_39_2\example_design\par\icon_flist.txt
02_ddr3_test\mig_39_2\example_design\par\icon_readme.txt
02_ddr3_test\mig_39_2\example_design\par\icon_xmdf.tcl
02_ddr3_test\mig_39_2\example_design\par\ila.cdc
02_ddr3_test\mig_39_2\example_design\par\ila.gise
02_ddr3_test\mig_39_2\example_design\par\ila.ngc
02_ddr3_test\mig_39_2\example_design\par\ila.xco
02_ddr3_test\mig_39_2\example_design\par\ila_coregen.xco
02_ddr3_test\mig_39_2\example_design\par\ila_flist.txt
02_ddr3_test\mig_39_2\example_design\par\ila_readme.txt
02_ddr3_test\mig_39_2\example_design\par\ila_xmdf.tcl
02_ddr3_test\mig_39_2\example_design\par\iseconfig\example_top.xreport
02_ddr3_test\mig_39_2\example_design\par\iseconfig\test.projectmgr
02_ddr3_test\mig_39_2\example_design\par\ise_flow.bat
02_ddr3_test\mig_39_2\example_design\par\ise_run.txt
02_ddr3_test\mig_39_2\example_design\par\makeproj.bat
02_ddr3_test\mig_39_2\example_design\par\mem_interface_top.ut
02_ddr3_test\mig_39_2\example_design\par\par_usage_statistics.html
02_ddr3_test\mig_39_2\example_design\par\readme.txt
02_ddr3_test\mig_39_2\example_design\par\rem_files.bat
02_ddr3_test\mig_39_2\example_design\par\set_ise_prop.tcl
02_ddr3_test\mig_39_2\example_design\par\test.gise
02_ddr3_test\mig_39_2\example_design\par\test.xise
02_ddr3_test\mig_39_2\example_design\par\tmp\_xmsgs\pn_parser.xmsgs
02_ddr3_test\mig_39_2\example_design\par\usage_statistics_webtalk.html
02_ddr3_test\mig_39_2\example_design\par\vio.cdc
02_ddr3_test\mig_39_2\example_design\par\vio.gise
02_ddr3_test\mig_39_2\example_design\par\vio.ngc
02_ddr3_test\mig_39_2\example_design\par\vio.xco
02_ddr3_test\mig_39_2\example_design\par\vio_coregen.xco
02_ddr3_test\mig_39_2\example_design\par\vio_flist.txt
02_ddr3_test\mig_39_2\example_design\par\vio_readme.txt
02_ddr3_test\mig_39_2\example_design\par\vio_xmdf.tcl
02_ddr3_test\mig_39_2\example_design\par\webtalk.log
02_ddr3_test\mig_39_2\example_design\par\webtalk_pn.xml
02_ddr3_test\mig_39_2\example_design\par\xlnx_auto_0_xdb\cst.xbcd
02_ddr3_test\mig_39_2\example_design\par\xst\work\work.sdbl
02_ddr3_test\mig_39_2\example_design\par\xst\work\work.sdbx
02_ddr3_test\mig_39_2\example_design\par\_ngo\netlist.lst
02_ddr3_test\mig_39_2\example_design\par\_xmsgs\bitgen.xmsgs
02_ddr3_test\mig_39_2\example_design\par\_xmsgs\map.xmsgs
02_ddr3_test\mig_39_2\example_design\par\_xmsgs\ngdbuild.xmsgs
02_ddr3_test\mig_39_2\example_design\par\_xmsgs\par.xmsgs

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