Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and the ability to randomly change column addresses on each clock cycle during a burst cycle. This reference design provides the user with a baseline SDRAM Controller design. The user may modify the design to meet specific design requirements. This document provides information on how this design operates and shows the user where changes can be made to support other functionality.

sdram controller
sdram controller\sd_cnfg.v
sdram controller\sd_rfrsh.v
sdram controller\sd_sig.v
sdram controller\sd_state.v
sdram controller\sd_top.v

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