This is the sequence detector. Have a serial sequence is defined as the clock and the corresponding control signal, producing a stable single-bit output signal monitor means the corresponding clock input sequence level, monitoring the sequence of the existence of the default sequence, whether from the first few enter a start, as long as there is, always monitored. Monitoring to be marked.

Packet : 25811216detecter.rar filelist
x\half_clk.asm.rpt
x\half_clk.cdf
x\half_clk.done
x\half_clk.dpf
x\half_clk.epe.rpt
x\half_clk.epe.summary
x\half_clk.fit.rpt
x\half_clk.fit.smsg
x\half_clk.fit.summary
x\half_clk.flow.rpt
x\half_clk.hex
x\half_clk.hexout
x\half_clk.jbc
x\half_clk.map.rpt
x\half_clk.map.summary
x\half_clk.pin
x\half_clk.pof
x\half_clk.qpf
x\half_clk.qsf
x\half_clk.qws
x\half_clk.sim.rpt
x\half_clk.sof
x\half_clk.tan.rpt
x\half_clk.tan.summary
x\half_clk.v
x\half_clk.vwf
x\output_file.pof
x\db\half_clk.(0).cnf.cdb
x\db\half_clk.(0).cnf.hdb
x\db\half_clk.asm.qmsg
x\db\half_clk.cbx.xml
x\db\half_clk.cmp.cdb
x\db\half_clk.cmp.hdb
x\db\half_clk.cmp.kpt
x\db\half_clk.cmp.logdb
x\db\half_clk.cmp.qrpt
x\db\half_clk.cmp.rdb
x\db\half_clk.cmp.tdb
x\db\half_clk.cmp0.ddb
x\db\half_clk.dbp
x\db\half_clk.db_info
x\db\half_clk.eco.cdb
x\db\half_clk.eds_overflow
x\db\half_clk.epe.qmsg
x\db\half_clk.fit.qmsg
x\db\half_clk.fnsim.hdb
x\db\half_clk.fnsim.qmsg
x\db\half_clk.hier_info
x\db\half_clk.hif
x\db\half_clk.map.cdb
x\db\half_clk.map.hdb
x\db\half_clk.map.logdb
x\db\half_clk.map.qmsg
x\db\half_clk.pre_map.cdb
x\db\half_clk.pre_map.hdb
x\db\half_clk.psp
x\db\half_clk.rpp.qmsg
x\db\half_clk.rtlv.hdb
x\db\half_clk.rtlv_sg.cdb
x\db\half_clk.rtlv_sg_swap.cdb
x\db\half_clk.sgate.rvd
x\db\half_clk.sgate_sm.rvd
x\db\half_clk.sgdiff.cdb
x\db\half_clk.sgdiff.hdb
x\db\half_clk.sim.hdb
x\db\half_clk.sim.qmsg
x\db\half_clk.sim.rdb
x\db\half_clk.sim.vwf
x\db\half_clk.sld_design_entry.sci
x\db\half_clk.sld_design_entry_dsc.sci
x\db\half_clk.syn_hier_info
x\db\half_clk.tan.qmsg
x\db\wed.zsf
x\db
x

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