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gtx_interface_ip

  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-09-22
  • Size : 1.14mb
  • Downloaded :0次
  • Author :周召涛
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Introduction - If you have any usage issues, please Google them yourself
High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
Packet file list
(Preview for download)


gtx_interface_ip\coregen.cgp
................\coregen.log
................\create_gtx_interface_ip.tcl
................\edit_gtx_interface_ip.tcl
................\gtx_interface_ip\doc\v5_gtxwizard_ds601.pdf
................\................\...\v5_gtxwizard_ds601.pdf.1
................\................\...\v5_gtxwizard_gsg204.pdf
................\................\example_design\frame_check.v
................\................\..............\frame_gen.v
................\................\..............\gtx_attributes.ucf
................\................\..............\gtx_interface_ip_top.ucf
................\................\..............\gtx_interface_ip_top.v
................\................\..............\tx_sync.v
................\................\gtx_interface_ip.pf
................\................\implement\chipscope_project.cpj
................\................\.........\data_vio.edn
................\................\.........\data_vio.ncf
................\................\.........\icon.ncf
................\................\.........\icon.ngc
................\................\.........\ila.ncf
................\................\.........\ila.ngc
................\................\.........\implement.bat
................\................\.........\implement.sh
................\................\.........\implement_synplify.bat
................\................\.........\implement_synplify.sh
................\................\.........\shared_vio.ncf
................\................\.........\shared_vio.ngc
................\................\.........\synplify.prj
................\................\.........\xst.prj
................\................\.........\xst.scr
................\................\simulation\demo_tb.v
................\................\..........\functional\simulate_isim.bat
................\................\..........\..........\simulate_isim.sh
................\................\..........\..........\simulate_mti.do
................\................\..........\..........\wave_isim.tcl
................\................\..........\..........\wave_mti.do
................\................\v5_gtxwizard_readme.txt
................\gtx_interface_ip.gise
................\gtx_interface_ip.v
................\gtx_interface_ip.veo
................\gtx_interface_ip.xco
................\gtx_interface_ip.xise
................\gtx_interface_ip_flist.txt
................\gtx_interface_ip_tile.v
................\gtx_interface_ip_xmdf.tcl
................\tmp\_cg\xil_89788_5.in
................\...\...\xil_89788_5.out
................\...\.xmsgs\pn_parser.xmsgs
................\_xmsgs\cg.xmsgs
................\......\pn_parser.xmsgs
................\gtx_interface_ip\simulation\functional
................\................\doc
................\................\example_design
................\................\implement
................\................\simulation
................\tmp\_cg
................\...\_xmsgs
................\gtx_interface_ip
................\tmp
................\_xmsgs
gtx_interface_ip
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