Wang Jinming prepared Verilog HDL Programming Guide book, examples of the original code, suitable for beginners.

Packet : 69491756source.rar filelist
source\examples.pdf
source\chap3\adder4.v
source\chap3\adder_tp.v
source\chap3\aoi.v
source\chap3\count4.v
source\chap3\count4_tp.v
source\chap3\adder4.acf
source\chap3\adder4.ndb
source\chap3\adder4.hif
source\chap3\transcript
source\chap3\modelsim.ini
source\chap3\tcl_stacktrace.txt
source\chap3\work\_info
source\chap5\adder.v
source\chap5\adder16.v
source\chap5\alu.v
source\chap5\block.v
source\chap5\buried_ff.v
source\chap5\compile.v
source\chap5\count.v
source\chap5\count60.v
source\chap5\decode4_7.v
source\chap5\loop1.v
source\chap5\loop2.v
source\chap5\loop3.v
source\chap5\mult_for.v
source\chap5\mult_repeat.v
source\chap5\mux21_1.v
source\chap5\mux21_2.v
source\chap5\mux4_1.v
source\chap5\mux_casez.v
source\chap5\non_block.v
source\chap5\test.v
source\chap5\voter7.v
source\chap5\wave1.v
source\chap5\wave2.v
source\chap6\transcript
source\chap6\modelsim.ini
source\chap6\alutask.v
source\chap6\alu_tp.v
source\chap6\code_83.v
source\chap6\count.v
source\chap6\funct.v
source\chap6\funct_tp.v
source\chap6\paral1.v
source\chap6\paral2.v
source\chap6\serial1.v
source\chap6\serial2.v
source\chap6\work\_info
source\chap3\work
source\chap6\work
source\chap3
source\chap5
source\chap6
source

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