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decoder_7_SEG_1

  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-05-18
  • Size : 115kb
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  • Author :woo
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this files in Quartus 2 are decoder
Packet file list
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db\decoder_7_SEG_1.asm.qmsg
..\decoder_7_SEG_1.cmp.cdb
..\decoder_7_SEG_1.cmp.ddb
..\decoder_7_SEG_1.cmp.hdb
..\decoder_7_SEG_1.cmp.rdb
..\decoder_7_SEG_1.cmp.tdb
..\decoder_7_SEG_1.cmp0.ddb
..\decoder_7_SEG_1.db_info
..\decoder_7_SEG_1.eco.cdb
..\decoder_7_SEG_1.fit.qmsg
..\decoder_7_SEG_1.hier_info
..\decoder_7_SEG_1.hif
..\decoder_7_SEG_1.map.cdb
..\decoder_7_SEG_1.map.hdb
..\decoder_7_SEG_1.map.qmsg
..\decoder_7_SEG_1.pre_map.cdb
..\decoder_7_SEG_1.pre_map.hdb
..\decoder_7_SEG_1.psp
..\decoder_7_SEG_1.rtlv.hdb
..\decoder_7_SEG_1.rtlv_sg.cdb
..\decoder_7_SEG_1.rtlv_sg_swap.cdb
..\decoder_7_SEG_1.sgdiff.cdb
..\decoder_7_SEG_1.sgdiff.hdb
..\decoder_7_SEG_1.signalprobe.cdb
..\decoder_7_SEG_1.sld_design_entry.sci
..\decoder_7_SEG_1.sld_design_entry_dsc.sci
..\decoder_7_SEG_1.syn_hier_info
..\decoder_7_SEG_1.tan.qmsg
..\decoder_7_SEG_1_cmp.qrpt
cmp_state.ini
decoder_7_SEG_1.asm.rpt
decoder_7_SEG_1.cdf
decoder_7_SEG_1.done
decoder_7_SEG_1.fit.eqn
decoder_7_SEG_1.fit.rpt
decoder_7_SEG_1.fit.summary
decoder_7_SEG_1.flow.rpt
decoder_7_SEG_1.map.eqn
decoder_7_SEG_1.map.rpt
decoder_7_SEG_1.map.summary
decoder_7_SEG_1.pin
decoder_7_SEG_1.pof
decoder_7_SEG_1.psof
decoder_7_SEG_1.qpf
decoder_7_SEG_1.qsf
decoder_7_SEG_1.qws
decoder_7_SEG_1.sbi
decoder_7_SEG_1.sof
decoder_7_SEG_1.tan.rpt
decoder_7_SEG_1.tan.summary
decoder_7_SEG_1.v
decoder_7_SEG_1_1.pof
decoder_7_SEG_1_2.pof
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