div of Verilog development process, make a slight modification can be applied to specific projects which

Packet : 23825786div.rar filelist
div\ .ptf
div\ .v
div\ .vhd
div\ddiv.vwf
div\div.asm.rpt
div\div.bdf
div\div.done
div\div.dpf
div\div.fit.rpt
div\div.fit.smsg
div\div.fit.summary
div\div.flow.rpt
div\div.map.rpt
div\div.map.summary
div\div.pin
div\div.pof
div\div.qpf
div\div.qsf
div\div.qws
div\div.sim.rpt
div\div.sim.vwf
div\div.sof
div\div.tan.rpt
div\div.tan.summary
div\div.vwf
div\div1248.bsf
div\div1248.vhd
div\div2_4_8_16.bsf
div\div2_4_8_16.vhd
div\pci.bsf
div\pci.cmp
div\pci.html
div\pci.ppf
div\pci.vhd
div\pci.vho
div\pci.xml
div\sopc_builder_debug_log.txt
div\touch.bsf
div\touch.vhd
div\undo_redo.txt
div\Waveform1.vwf
div\db\div.(0).cnf.cdb
div\db\div.(0).cnf.hdb
div\db\div.(1).cnf.cdb
div\db\div.(1).cnf.hdb
div\db\div.(2).cnf.cdb
div\db\div.(2).cnf.hdb
div\db\div.(3).cnf.cdb
div\db\div.(3).cnf.hdb
div\db\div.asm.qmsg
div\db\div.cbx.xml
div\db\div.cmp.cdb
div\db\div.cmp.hdb
div\db\div.cmp.kpt
div\db\div.cmp.logdb
div\db\div.cmp.rdb
div\db\div.cmp.tdb
div\db\div.cmp0.ddb
div\db\div.dbp
div\db\div.db_info
div\db\div.eco.cdb
div\db\div.eds_overflow
div\db\div.fit.qmsg
div\db\div.hier_info
div\db\div.hif
div\db\div.map.cdb
div\db\div.map.hdb
div\db\div.map.logdb
div\db\div.map.qmsg
div\db\div.pre_map.cdb
div\db\div.pre_map.hdb
div\db\div.psp
div\db\div.rtlv.hdb
div\db\div.rtlv_sg.cdb
div\db\div.rtlv_sg_swap.cdb
div\db\div.sgdiff.cdb
div\db\div.sgdiff.hdb
div\db\div.signalprobe.cdb
div\db\div.sim.hdb
div\db\div.sim.qmsg
div\db\div.sim.rdb
div\db\div.sim.vwf
div\db\div.sld_design_entry.sci
div\db\div.sld_design_entry_dsc.sci
div\db\div.syn_hier_info
div\db\div.tan.qmsg
div\db\wed.zsf
div\db
div\.sopc_builder\install.ptf
div\.sopc_builder
div

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