Introduction - If you have any usage issues, please Google them yourself
module b_c(dout,clk,clr,din)
output dout
input [3:0] din
input clk,clr
reg dout
reg [3:0] q
reg [1:0] cnt
always@(posedge clk)
begin
cnt<=cnt+1
if(clr)
q<=0
else
begin
if(cnt>0)
q[3:1]<=q[2:0]
else
if(cnt==0) q<=din
end
dout<=q[3]
end
endmodule