Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated

Packet : 59564336fifo_syn.rar filelist
FIFO_Syn\FIFO_Buffer.v
FIFO_Syn\FIFO_Syn.cr.mti
FIFO_Syn\FIFO_Syn.mpf
FIFO_Syn\t_FIFO_Buffer.v
FIFO_Syn\vsim.wlf
FIFO_Syn\work\@f@i@f@o_@buffer\verilog.asm
FIFO_Syn\work\@f@i@f@o_@buffer\_primary.dat
FIFO_Syn\work\@f@i@f@o_@buffer\_primary.vhd
FIFO_Syn\work\@f@i@f@o_@buffer
FIFO_Syn\work\t_@f@i@f@o_@buffer\verilog.asm
FIFO_Syn\work\t_@f@i@f@o_@buffer\_primary.dat
FIFO_Syn\work\t_@f@i@f@o_@buffer\_primary.vhd
FIFO_Syn\work\t_@f@i@f@o_@buffer
FIFO_Syn\work\_info
FIFO_Syn\work
FIFO_Syn

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