Frequency counter FPGA-based design. By using FPGA, VHDL programming, the use of FPGA (field programmable gate array) chip design an 8-bit digital precision frequency meter, etc., the frequency meter measurement range of 0-100MHZ, using QUARTUS II integrated development environment for editing, synthesis, simulation waveforms, and downloaded to the CPLD device, the actual circuit testing, simulation and experimental results show that the frequency counter has a higher availability and reliability.

Frequency counter\1.bdf
.................\2.bdf
.................\3.bdf
.................\4.bdf
.................\5.bdf
.................\6.bdf
.................\a.asm.rpt
.................\a.done
.................\a.dpf
.................\a.eda.rpt
.................\a.fit.eqn
.................\a.fit.rpt
.................\a.fit.smsg
.................\a.fit.summary
.................\a.flow.rpt
.................\a.map.eqn
.................\a.map.rpt
.................\a.map.summary
.................\a.pin
.................\a.pof
.................\a.qpf
.................\a.qsf
.................\a.qws
.................\a.sim.rpt
.................\a.sof
.................\a.tan.rpt
.................\a.tan.summary
.................\a.vwf
.................\a_assignment_defaults.qdf
.................\a_description.txt
.................\CNT.bsf
.................\CNT.vhd
.................\CNT.vwf
.................\CNT10.bsf
.................\CNT10.vhd
.................\CNT10.vwf
.................\db\a.asm.qmsg
.................\..\a.asm_labs.ddb
.................\..\a.cbx.xml
.................\..\a.cmp.cdb
.................\..\a.cmp.hdb
.................\..\a.cmp.kpt
.................\..\a.cmp.logdb
.................\..\a.cmp.rdb
.................\..\a.cmp.tdb
.................\..\a.cmp0.ddb
.................\..\a.cmp2.ddb
.................\..\a.db_info
.................\..\a.eco.cdb
.................\..\a.eda.qmsg
.................\..\a.eds_overflow
.................\..\a.fit.qmsg
.................\..\a.fnsim.hdb
.................\..\a.fnsim.qmsg
.................\..\a.hier_info
.................\..\a.hif
.................\..\a.lpc.html
.................\..\a.lpc.rdb
.................\..\a.lpc.txt
.................\..\a.map.cdb
.................\..\a.map.hdb
.................\..\a.map.logdb
.................\..\a.map.qmsg
.................\..\a.pre_map.cdb
.................\..\a.pre_map.hdb
.................\..\a.rpp.qmsg
.................\..\a.rtlv.hdb
.................\..\a.rtlv_sg.cdb
.................\..\a.rtlv_sg_swap.cdb
.................\..\a.sgate.rvd
.................\..\a.sgate_sm.rvd
.................\..\a.sgdiff.cdb
.................\..\a.sgdiff.hdb
.................\..\a.sim.hdb
.................\..\a.sim.qmsg
.................\..\a.sim.rdb
.................\..\a.sim.vwf
.................\..\a.simfam
.................\..\a.sim_ori.vwf
.................\..\a.sld_design_entry.sci
.................\..\a.sld_design_entry_dsc.sci
.................\..\a.syn_hier_info
.................\..\a.tan.qmsg
.................\..\a.tis_db_list.ddb
.................\..\a.tmw_info
.................\..\a_global_asgn_op.abo
.................\..\mux_3nc.tdf
.................\..\mux_joc.tdf
.................\..\prev_cmp_a.asm.qmsg
.................\..\prev_cmp_a.eda.qmsg
.................\..\prev_cmp_a.fit.qmsg
.................\..\prev_cmp_a.map.qmsg
.................\..\prev_cmp_a.qmsg
.................\..\prev_cmp_a.sim.qmsg
.................\..\prev_cmp_a.tan.qmsg
.................\..\wed.wsf
.................\DISPLAY.bsf
.................\DISPLAY.vhd
.................\DISPLAY.vwf
.................\incremental_db\compiled_partitions\a.root_partition.map.kpt

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