VHDL-FPGA-Verilog List Page 3973

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[VHDL-FPGA-VerilogSdram_Controller

Description: SDRAM controller code to realize SDRAM control
Platform: Verilog | Size: 15664128 | Author: 坤坤55 | Hits: 0

[VHDL-FPGA-VerilogLED_8255A

Description: Use Verilog to imitate 8255A operation mode to control LED, only schematic diagram, no V file
Platform: VHDL | Size: 125952 | Author: 一流大学渣 | Hits: 0

[VHDL-FPGA-VerilogEP4CE6

Description: Hardware schematic diagram of ep4ce6, including PCB diagram
Platform: C/C++ | Size: 58368 | Author: zui135 | Hits: 0

[VHDL-FPGA-Verilog频率计3

Description: 1. It can correctly display the input signal frequency; 2. The frequency range of measurement is 1Hz ~ 99999hz; 3. The measurement results are displayed in decimal; 4. It can measure signal frequency with small amplitude; 5. It has the function of automatically refreshing the output data (e.g. once in 5S); 6. Self checking module (such as generating 100Hz calibration square wave);
Platform: Multisim | Size: 483328 | Author: 独行的云 | Hits: 0

[VHDL-FPGA-Verilogeetop.cn_nand_flash_ctl

Description: Nand_flash code explanation, may not be very detailed, but can achieve basic functions, for your reference
Platform: Quartus II | Size: 4096 | Author: wind_mark | Hits: 0

[VHDL-FPGA-VerilogFIR-Filter-using-Precomputation-Block-master

Description: Based on vivado 2017.4, this program multiplies the number of two fixed points and compiles the simulation file testbench
Platform: VHDL | Size: 2048 | Author: 重黎火 | Hits: 0

[VHDL-FPGA-VerilogRGB

Description: RGB breathing lamp lighting program based on nexys4 DDR has been verified on the board
Platform: VHDL | Size: 610304 | Author: 重黎火 | Hits: 0

[VHDL-FPGA-Verilogtest2017_4

Description: Based on vivado 2017.4 using switch to change the light of LED lamp and cooperate with testbench simulation
Platform: VHDL | Size: 1105920 | Author: 重黎火 | Hits: 0

[VHDL-FPGA-Verilogisenexys4xadc

Description: Constraint file of nexys4ddr board, programming interface can be customized
Platform: VHDL | Size: 2958336 | Author: 重黎火 | Hits: 0

[VHDL-FPGA-Verilogcount_clk

Description: Realize clock frequency division function
Platform: VHDL | Size: 41984 | Author: 光机所小孙 | Hits: 0

[VHDL-FPGA-VerilogCPU_SELF_monocycle

Description: A single cycle CPU is designed, which can realize the basic R-type and J-type instruction function operation.
Platform: Verilog | Size: 4882432 | Author: 张欣宇 | Hits: 0

[VHDL-FPGA-Verilog0_17_EEPROM

Description: The reading and writing configuration operation of E2PROM is implemented on FPGA, with simulation model using Modelsim
Platform: Verilog | Size: 7124992 | Author: ZDCHXGG | Hits: 0
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