actel fpga Verilog D latch

D_latch\designer\impl1\designer.log
.......\........\.....\D_latch.adb
.......\........\.....\D_latch.dat
.......\........\.....\.........tf\verify.log
.......\........\.....\D_latch.ide_des
.......\........\.....\D_latch.pdb
.......\........\.....\D_latch.pdb.depends
.......\........\.....\D_latch.stp
.......\........\.....\D_latch.tcl
.......\D_latch.prj
.......\hdl\D_latch.v
.......\simulation\modelsim.ini
.......\.martgen\smartgen.aws
.......\.ynthesis\D_latch.areasrr
.......\.........\D_latch.edn
.......\.........\D_latch.fse
.......\.........\D_latch.htm
.......\.........\D_latch.map
.......\.........\D_latch.pdc
.......\.........\D_latch.sap
.......\.........\D_latch.sdf
.......\.........\D_latch.so
.......\.........\D_latch.srd
.......\.........\D_latch.srm
.......\.........\D_latch.srr
.......\.........\D_latch.srs
.......\.........\D_latch.szr
.......\.........\D_latch.tlg
.......\.........\D_latch_sdc.sdc
.......\.........\D_latch_syn.prj
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\.yntmp\D_latch.plg
.......\.........\......\D_latch_flink.htm
.......\.........\......\D_latch_srr.htm
.......\.........\......\D_latch_toc.htm
.......\.........\......\sap.log
.......\viewdraw\vf\project.lst
.......\........\viewdraw.ini
.......\designer\impl1\D_latch.dtf
.......\........\.....\simulation
.......\........\impl1
.......\synthesis\backup
.......\.........\coreip
.......\.........\syntmp
.......\viewdraw\sch
.......\........\sym
.......\........\vf
.......\........\wir
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\hdl
.......\phy_synthesis
.......\simulation
.......\smartgen
.......\stimulus
.......\synthesis
.......\viewdraw
D_latch

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