This is the company I used the sparten3 Xilinx development boards, ISE Integrated Development Environment, Using VHDL development of the full-duplex serial communication program, for your reference, learning together.

Packet : 69491701myuart.rar filelist
myUART\baud_test.ant
myUART\baud_test.jhd
myUART\baud_test.tbw
myUART\baud_test.vhw
myUART\baud_test.xwv
myUART\baud_test.xwv_bak
myUART\baud_test_beh.prj
myUART\baud_test_bencher.prj
myUART\baud_test_isim_beh.exe
myUART\CLK_DIV.vhd
myUART\gg.ant
myUART\gg.jhd
myUART\gg.tbw
myUART\gg.vhw
myUART\gg.xwv
myUART\gg.xwv_bak
myUART\gg_beh.prj
myUART\gg_bencher.prj
myUART\gg_isim_beh.exe
myUART\isim\work\baud\devider.h
myUART\isim\work\baud\mingw\devider.obj
myUART\isim\work\baud\mingw
myUART\isim\work\baud
myUART\isim\work\baud_test\mingw\testbench_arch.obj
myUART\isim\work\baud_test\mingw
myUART\isim\work\baud_test\testbench_arch.h
myUART\isim\work\baud_test\xsimtestbench_arch.cpp
myUART\isim\work\baud_test
myUART\isim\work\gg\mingw\testbench_arch.obj
myUART\isim\work\gg\mingw
myUART\isim\work\gg\testbench_arch.h
myUART\isim\work\gg\xsimtestbench_arch.cpp
myUART\isim\work\gg
myUART\isim\work\hdllib.ref
myUART\isim\work\hdpdeps.ref
myUART\isim\work\sub00\vhpl00.vho
myUART\isim\work\sub00\vhpl01.vho
myUART\isim\work\sub00\vhpl02.vho
myUART\isim\work\sub00\vhpl03.vho
myUART\isim\work\sub00\vhpl04.vho
myUART\isim\work\sub00\vhpl05.vho
myUART\isim\work\sub00
myUART\isim\work
myUART\isim
myUART\isim.cmd
myUART\isim.hdlsourcefiles
myUART\isim.log
myUART\isim.tmp_save\_1
myUART\isim.tmp_save
myUART\isimwavedata.xwv
myUART\myUART.ise
myUART\myUART.ise_ISE_Backup
myUART\pepExtractor.prj
myUART\RBUF.vhd
myUART\results.txt
myUART\TBUF.vhd
myUART\top.bgn
myUART\top.bld
myUART\top.cmd_log
myUART\top.drc
myUART\top.lso
myUART\top.ncd
myUART\top.ngc
myUART\top.ngd
myUART\top.ngr
myUART\top.pad
myUART\top.par
myUART\top.pcf
myUART\top.prj
myUART\top.stx
myUART\top.syr
myUART\top.twr
myUART\top.twx
myUART\top.ucf
myUART\top.unroutes
myUART\top.ut
myUART\top.vhd
myUART\top.xpi
myUART\top.xst
myUART\top_last_par.ncd
myUART\top_map.mrp
myUART\top_map.ncd
myUART\top_map.ngm
myUART\top_pad.csv
myUART\top_pad.txt
myUART\TOP_summary.html
myUART\xilinxsim.ini
myUART\xst\dump.xst\top.prj\ngx\notopt
myUART\xst\dump.xst\top.prj\ngx\opt
myUART\xst\dump.xst\top.prj\ngx
myUART\xst\dump.xst\top.prj
myUART\xst\dump.xst
myUART\xst\projnav.tmp
myUART\xst\work\hdllib.ref
myUART\xst\work\hdpdeps.ref
myUART\xst\work\sub00\vhpl00.vho
myUART\xst\work\sub00\vhpl01.vho
myUART\xst\work\sub00\vhpl02.vho
myUART\xst\work\sub00\vhpl03.vho
myUART\xst\work\sub00\vhpl04.vho
myUART\xst\work\sub00\vhpl05.vho
myUART\xst\work\sub00\vhpl06.vho
myUART\xst\work\sub00\vhpl07.vho
myUART\xst\work\sub00
myUART\xst\work
myUART\xst
myUART\_ngo\netlist.lst
myUART\_ngo
myUART\_xmsgs\fuse.xmsgs
myUART\_xmsgs\vhpcomp.xmsgs
myUART\_xmsgs
myUART

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