This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL). The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.

cppll.mdl
dpll.mdl
dpll_fixpt.mdl
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license.txt
linearpll.mdl
plldemo.m
powerpll.mdl

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