Introduction - If you have any usage issues, please Google them yourself
verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... and test module used to verify the state is working
Packet : 107215780xcv.rar filelist
xcv\test.v
xcv\work\xcv\verilog.asm
xcv\work\xcv\_primary.dat
xcv\work\xcv\_primary.vhd
xcv\work\xcv_@top\verilog.asm
xcv\work\xcv_@top\_primary.dat
xcv\work\xcv_@top\_primary.vhd
xcv\work\_info
xcv\xcv.v
xcv\work\xcv
xcv\work\xcv_@top
xcv\work
xcv