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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1mb
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  • Author :tom
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Introduction - If you have any usage issues, please Google them yourself
Frequency Counter realized with Altera EPM7128SLC84-15. It can measure frequecy, cycle and pulse width of TTL sigals.
Packet file list
(Preview for download)
freqm
.....\cmp_state.ini
.....\counter
.....\.......\cmp_state.ini
.....\.......\counter.asm.rpt
.....\.......\counter.bsf
.....\.......\counter.done
.....\.......\counter.fit.eqn
.....\.......\counter.fit.rpt
.....\.......\counter.fit.summary
.....\.......\counter.flow.rpt
.....\.......\counter.map.eqn
.....\.......\counter.map.rpt
.....\.......\counter.map.summary
.....\.......\counter.pin
.....\.......\counter.pof
.....\.......\counter.qpf
.....\.......\counter.qsf
.....\.......\counter.qws
.....\.......\counter.sim.rpt
.....\.......\counter.tan.rpt
.....\.......\counter.tan.summary
.....\.......\counter.vhd
.....\.......\counter.vhd.bak
.....\.......\counter.vwf
.....\.......\db
.....\.......\..\counter.asm.qmsg
.....\.......\..\counter.cmp.cdb
.....\.......\..\counter.cmp.ddb
.....\.......\..\counter.cmp.hdb
.....\.......\..\counter.cmp.rdb
.....\.......\..\counter.cmp.tdb
.....\.......\..\counter.db_info
.....\.......\..\counter.fit.qmsg
.....\.......\..\counter.hier_info
.....\.......\..\counter.hif
.....\.......\..\counter.map.cdb
.....\.......\..\counter.map.hdb
.....\.......\..\counter.map.qmsg
.....\.......\..\counter.pre_map.hdb
.....\.......\..\counter.project.hdb
.....\.......\..\counter.rpp.qmsg
.....\.......\..\counter.rtlv.hdb
.....\.......\..\counter.rtlv_sg.cdb
.....\.......\..\counter.rtlv_sg_swap.cdb
.....\.......\..\counter.sgate.rvd
.....\.......\..\counter.sgdiff.cdb
.....\.......\..\counter.sgdiff.hdb
.....\.......\..\counter.sim.hdb
.....\.......\..\counter.sim.qmsg
.....\.......\..\counter.sim.rdb
.....\.......\..\counter.sim.vwf
.....\.......\..\counter.sld_design_entry.sci
.....\.......\..\counter.sld_design_entry_dsc.sci
.....\.......\..\counter.syn_hier_info
.....\.......\..\counter.tan.qmsg
.....\.......\..\counter_cmp.qrpt
.....\.......\..\counter_sim.qrpt
.....\.......\sim.cfg
.....\counter.bsf
.....\counter.vhd
.....\db
.....\..\add_sub_4ph.tdf
.....\..\add_sub_snh.tdf
.....\..\freqm.asm.qmsg
.....\..\freqm.cmp.cdb
.....\..\freqm.cmp.ddb
.....\..\freqm.cmp.hdb
.....\..\freqm.cmp.rdb
.....\..\freqm.cmp.tdb
.....\..\freqm.db_info
.....\..\freqm.fit.qmsg
.....\..\freqm.fld
.....\..\freqm.hier_info
.....\..\freqm.hif
.....\..\freqm.map.cdb
.....\..\freqm.map.hdb
.....\..\freqm.map.qmsg
.....\..\freqm.pre_map.hdb
.....\..\freqm.project.hdb
.....\..\freqm.rpp.qmsg
.....\..\freqm.rtlv.hdb
.....\..\freqm.rtlv_sg.cdb
.....\..\freqm.rtlv_sg_swap.cdb
.....\..\freqm.sgate.rvd
.....\..\freqm.sgdiff.cdb
.....\..\freqm.sgdiff.hdb
.....\..\freqm.sim.hdb
.....\..\freqm.sim.qmsg
.....\..\freqm.sim.rdb
.....\..\freqm.sim.vwf
.....\..\freqm.sld_design_entry.sci
.....\..\freqm.sld_design_entry_dsc.sci
.....\..\freqm.syn_hier_info
.....\..\freqm.tan.qmsg
.....\..\freqm_cmp.qrpt
.....\..\freqm_sim.qrpt
.....\dispselector
.....\............\cmp_state.ini
.....\............\db
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