Verilog digital system design: RTL synthesis, test and verification platform-Zainalabedin Navabi-attached CD-ROM source

Designs
.......\Chapter 1
.......\.........\chap1counter.v
.......\.........\Chap1CounterTester.v
.......\.........\confn.v
.......\.........\dlatch.v
.......\.........\dreg.v
.......\.........\latchtest.v
.......\.........\parity.v
.......\.........\srlatch.v
.......\Chapter 2
.......\.........\ALU.v
.......\.........\ALUTester.v
.......\.........\Counter4.v
.......\.........\Counter4Tester.v
.......\.........\Detector110.v
.......\.........\Detector110Tester.v
.......\.........\flop.v
.......\.........\FlopTester.v
.......\.........\MultiplexerA.v
.......\.........\MultiplexerA2to1.v
.......\.........\MultiplexerB.v
.......\.........\MultiplexerC.v
.......\.........\MultiplexerD.v
.......\.........\MultiplexerE.v
.......\.........\MultiplexerTester.v
.......\.........\Mux8.v
.......\.........\Mux8Tester.v
.......\.........\ShiftRegister.v
.......\.........\ShiftRegisterTester.v
.......\.........\Synchronizer.v
.......\.........\SynchronizerTester.v
.......\Chapter 3
.......\.........\Flipflop.v
.......\.........\FlipflopAssign.v
.......\.........\FlipflopAssignTester.v
.......\.........\FlipflopTester.v
.......\.........\Fulladder.v
.......\.........\FulladderTester.v
.......\.........\MemoryTest.v
.......\.........\Mux2ti1TestA.v
.......\.........\Mux2to1.v
.......\.........\Mux2to1BTest.v
.......\.........\Mux2to1Multiple.v
.......\.........\Mux2to1Net.v
.......\.........\Mux2to1TestC.v
.......\.........\Mux2to1Tester.v
.......\.........\NumberTest.v
.......\.........\OperatorTest.v
.......\.........\SignTest.v
.......\Chapter 4
.......\.........\add_1bit.v
.......\.........\add_1bit_blocking.v
.......\.........\add_1bit_f.v
.......\.........\add_1bit_p.v
.......\.........\add_1bit_p2p.v
.......\.........\add_1bit_p_named.v
.......\.........\add_4bit.v
.......\.........\add_4bit_gen.v
.......\.........\add_4bit_genif.v
.......\.........\add_4bit_p2p.v
.......\.........\add_4bit_vec.v
.......\.........\Anding.v
.......\.........\AndingTest.v
.......\.........\maj3_p.v
.......\.........\multi_alu.v
.......\.........\multi_alu_test.v
.......\.........\priority_encoder.v
.......\.........\quad_mux2_1.v
.......\.........\test_add_1bit_blocking.v
.......\.........\test_add_1bit_p.v
.......\.........\test_add_4bit.v
.......\.........\test_maj3_p.v
.......\.........\test_priority_encoder.v
.......\.........\test_quad_mux2_1.v
.......\.........\test_xor3.v
.......\.........\transcript
.......\.........\TriMux.v
.......\.........\TriMuxTest.v
.......\.........\xor3_behavioral.v
.......\.........\xor3_p.v
.......\Chapter 5
.......\.........\counter.v
.......\.........\d_ff.v
.......\.........\d_ff_hold.v
.......\.........\d_ff_setup.v
.......\.........\d_ff_sr_Asynch.v
.......\.........\d_ff_sr_Synch.v
.......\.........\d_ff__setup_hold_width_period.v
.......\.........\gray_ounter.v
.......\.........\latch.v
.......\.........\latch_p.v
.......\.........\latch_w.v
.......\.........\lfsr1.v
.......\.........\lfsr2.v
.......\.........\mealy.dat
.......\.........\mealy_detector2.v
.......\.........\mealy_detector6.v
.......\.........\mealy_detector7.v
.......\.........\mem.dat

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